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preliminary specification: version 1.0 may1995 data sheet SAA7378GP single chip digital servo processor and compact disc decoder (cd7) philips semiconductors integrated circuits
philips semiconductors preliminary speci?cation: version 1.0 may 1995 2 digital servo processor and compact disc decoder (cd7) SAA7378GP 1. fea tures ? single speed mode. ? full error correction strategy, t = 2 and e = 4. ? all standard decoder functions implemented digitally on chip. ? fifo over?ow concealment for rotational shock resistance. ? digital audio interface (ebu), audio only. ? 2 - 4 times oversampling integrated digital ?lter. ? audio data peak level detection. ? kill interface for dac deactivation during digital silence. ? all tda1301 (dsic2) digital servo functions, plus extra hi-level functions. ? low focus noise. ? communication via tda1301/saa7345 compatible bus. ? on chip clock multiplier allows the use of 8.4672mhz crystal. 2. general description cd7 (SAA7378GP) is a single chip combining the functions of a cd decoder ic and digital servo ic. the decoder part is based on cd6 (saa7345gp) with an improved error correction strategy; the servo part is based on dsic2 (tda1301t) with improvements incorporated. 3. quick reference da t a 4. ordering informa tion note 1. when using reflow soldering it is recommended that the dry packing instructions in the " quality reference pocketbook " are followed. the pocketbook can be ordered using the code 9398 510 34011. supply of this compact disc ic does not convey an implied license under any patent right to use this ic in any compact disc application. symbol parameter min typ max unit v dd supply voltage 3.4 5.0 5.5 v i dd supply current - 49 - ma f xtal crystal frequency 8 8.4672 35 mhz t amb operating ambient temperature 5 - +70 c t stg storage temperature -55 - +125 c extended type number package pins pin position material code SAA7378GP 64 qfp plastic sot393-1
philips semiconductors preliminary speci?cation: version 1.0 may 1995 3 digital servo processor and compact disc decoder (cd7) SAA7378GP vss4 vssa1 iref islice hfref hfin digital pll demodulator efm crin crout cl11 cl16 test5 timing scl sda rab micro- processor dobm sram ram addresser versatile pins interface audio processor kill peak detect motor control error corrector interface ebu interface flags test test1 test2 reset moto1 moto2 cflg sclk wclk data test8 kill v1 v2 v3 v4 v5 vrl d1 front end serial data test10 d2 d3 d4 adc pre- processing vref generator control function control part output stages micro processor inteface decoder interface vrh ra fo sl ldon r1 r2 vssa2 vdda1 vdda2 vss1 vss2 vss3 subcode processor test7 test6 ireft sild test3 cl4 test4 selpll vssa3 vdd1p vdd2p vdd3c figure 1 functional block diagram test9
philips semiconductors preliminary speci?cation: version 1.0 may 1995 4 digital servo processor and compact disc decoder (cd7) SAA7378GP 5. pin description symbol pin description v ssa 1 1 analogue supply* v dda 1 2 analogue supply* d1 3 unipolar current input (central diode signal input) d2 4 unipolar current input (central diode signal input) d3 5 unipolar current input (central diode signal input) v rl 6 reference input for adc d4 7 unipolar current input (central diode signal input) r1 8 unipolar current input (satellite diode signal input) r2 9 unipolar current input (satellite diode signal input) ireft 10 current reference for calibration adc v rh 11 reference output from adc v ssa 2 12 analogue supply* selpll 13 selects whether internal clock multiplier pll is used islice 14 current feedback from data slicer hfin 15 comparator signal input v ssa 3 16 analogue supply* hfref 17 comparator common mode input iref 18 reference current pin (nominally v dd /2) v dda 2 19 analogue supply* test1 20 test control input; this pin should be tied low crin 21 crystal/resonator input crout 22 crystal/resonator output test2 23 test control input; this pin should be tied low cl16 24 16.9344 mhz system clock output cl11 25 11.2896 mhz or 5.6448mhz clock output (tri-state) ra 26 radial actuator output fo 27 focus actuator output sl 28 sledge control output test3 29 test control input; this pin should be tied low v dd 1 p 30 digital supply periphery* dobm 31 bi-phase mark output (externally buffered) (tri-state) v ss 1 32 digital supply* moto1 33 motor output 1; versatile (tri-state) moto2 34 motor output 2; versatile (tri-state) test4 35 test output pin; this pin should be left unconnected test5 36 test output pin; this pin should be left unconnected
philips semiconductors preliminary speci?cation: version 1.0 may 1995 5 digital servo processor and compact disc decoder (cd7) SAA7378GP * note: all supply pins must be connected to the same external power supply voltage. test6 37 test input; this pin should be tied low test7 38 test output pin; this pin should be left unconnected v ss 2 39 digital supply* v5 40 versatile output pin v4 41 versatile output pin v3 42 versatile output pin (open drain) kill 43 kill output - programmable (open drain) test8 44 test output pin; this pin should be left unconnected data 45 serial data output (tri-state) wclk 46 word clock output (tri-state) v dd 2 p 47 digital supply periphery* sclk 48 serial bit clock output (tri-state) v ss 3 49 digital supply* cl4 50 4.2336 mhz m p clock output sda 51 m p interface data i/o line (open drain output) scl 52 m p interface clock line rab 53 m p interface r/ w and load control line sild 54 m p interface r/w and load control line n/c 55 no connection v ss 4 56 digital supply* reset 57 power-on reset input (active low) test9 58 test output pin; this pin should be left unconnected v dd 3 c 59 digital supply core* test10 60 test output pin; this pin should be left unconnected cflg 61 correction ?ag output (open drain) v1 62 versatile input pin v2 63 versatile input pin ldon 64 laser drive on output (open drain) symbol pin description
philips semiconductors preliminary speci?cation: version 1.0 may 1995 6 digital servo processor and compact disc decoder (cd7) SAA7378GP hfref 17 iref 18 v dda 219 test1 20 crin 21 crout 22 test2 23 cl16 24 cl11 25 ra 26 fo 27 sl 28 test3 29 v dd 1 p 30 dobm 31 v ss 132 64 ldon 63 v2 62 v1 61 cflg 60 test10 59 v dd 3 c 58 test9 57 reset 56 v ss 4 55 nc 54 sild 53 rab 52 scl 51 sda 50 cl4 49 v ss 3 v ssa 11 v dda 12 d1 3 d2 4 d3 5 v rl 6 d4 7 r1 8 r2 9 ireft 10 v rh 11 v ssa 212 selpll 13 islice 14 hfin 15 v ssa 316 48 sclk 47 v dd 2 p 46 wclk 45 data 44 test8 43 kill 42 v3 41 v4 40 v5 39 v ss 2 38 test7 37 test6 36 test5 35 test4 34 moto2 33 moto1 saa7378 figure 2 pinning diagram
philips semiconductors preliminary speci?cation: version 1.0 may 1995 7 digital servo processor and compact disc decoder (cd7) SAA7378GP 6. limiting v alues in accordance with the absolute maximum rating system (iec 134). notes: 1) all vdd and vss connections must be made externally to the same power supply. 2) equivalent to discharging a 100pf capacitor via a 1.5k w series resistor with a rise time of 15ns. 3) equivalent to discharging a 200pf capacitor via a 2.5 m h series inductor. symbol parameter conditions min max unit v dd supply voltage note 1 -0.5 +6.5 v v i(max) maximum input voltage (any input) -0.5 v dd + 0.5 v v o output voltage (any output) -0.5 +6.5 v vdd diff difference between v dda and v ddd 0.25 v i o output current (continuous) 20 ma i ik dc input diode current (continuous) 20 ma t amb operating ambient temperature 5 +70 c t stg storage temperature -55 +125 c v es1 electrostatic handling note 2 -2000 +2000 v v es2 electrostatic handling note 3 -200 +200 v
philips semiconductors preliminary speci?cation: version 1.0 may 1995 8 digital servo processor and compact disc decoder (cd7) SAA7378GP 7. functional description of the decoder p art 7.1 principle operation modes of the decoder part the decoding part operates at single speed and supports a full audio specification. a simplified data flow through the decoder part is shown in figure 5. 7.1.1 crystal frequency selection the saa7378 which has an internal phase locked loop clock multiplier, can be used with 33.8688, 16.9344 or 8.4672mhz crystal frequencies by setting register b and selpll as shown below. the internal clock multiplier, controlled by selpll, should only be used if an 8.4672mhz crystal, ceramic resonator or external clock is present. note: the cl11 output is a 5.6448mhz clock if a 16.9344mhz external clock is used. 7.1.2 standby modes the saa7378 may be placed in two standby modes, (note that the device core is still active), selected by register b : standby 1 : "cd-stop" mode. most i/o functions are switched off. standby 2: "cd-pause" mode. audio output features are switched off, but the motor loop, the motor output and the subcode interfaces remain active. this is also called a "hot pause". in the standby modes the various pins will have following values: moto1, moto2: put in hi-z, pwm mode (standby 1 and reset : operating in standby 2). put in hi-z, pdm mode (standby1 and reset: operating in standby 2). scl,sda, sild, rab: no interaction. normal operation continues. sclk, wclk, data, cl11, dobm: tri-state in both standby modes. normal operation continues after reset. crin, crout, cl16, cl4: no interaction. normal operation continues. v1, v2, v3, v4, v5, cflg: no interaction. normal operation continues. 7.2 crystal oscillator the crystal oscillator is a conventional 2 pin design operating at 8 mhz to 35 mhz. this oscillator is capable of working with ceramic resonators as well as with both fundamental and third overtone crystals. external components should be used to suppress the fundamental output of the third overtone crystals as shown below in figure 3. typical oscillation frequencies required are 8.4672mhz, 16.9344mhz or 33.8688mhz depending on the internal clock settings used and whether or not the clock multiplier is enabled. register b selpll crystal frequency (mhz) 00xx 0 33.8688 00xx 1 8.4672 01xx 0 16.9344
philips semiconductors preliminary speci?cation: version 1.0 may 1995 9 digital servo processor and compact disc decoder (cd7) SAA7378GP 3.3 m h figure 3 crystal oscillator circuits crin 8.4672mhz oscillator saa7378 8.4672mhz fundamental con?guration 33.8688mhz 3rd overtone con?guration crout 1nf 22pf 22pf 330 w crin 33.8688mhz oscillator 100k w saa7378 crout 10pf 10pf 330 w 100k w
philips semiconductors preliminary speci?cation: version 1.0 may 1995 10 digital servo processor and compact disc decoder (cd7) SAA7378GP 7.3 data slicer and clock regenerator the saa7378 has an integrated slice level comparator which can be clocked by the crystal frequency clock, or 8 times the crystal frequency clock (if selpll is set high while using an 8.4672mhz crystal, and register 4 is set to 0xxx ). the slice level is controlled by an internal current source applied to an external capacitor under the control of the digital phase-locked loop (dpll) . regeneration of the bit clock is achieved with an internal fully digital pll. no external components are required and the bit clock is not output. the pll has two registers (8 and 9) for selecting bandwidth and equalization. for certain applications an offtrack input is necessary. this is internally connected from the servo part (its polarity can be changed by the foc_parm1 parameter), but may be input via the v1 pin if selected by register c. if this flag is high, the saa7378 will assume that its servo part is following on the wrong track, and will flag all incoming hf data as incorrect. 7.4 demodulator 7.4.1 frame sync protection a double timing system is used to protect the demodulator from erroneous sync patterns in the serial data. the master counter is only reset if: - a sync coincidence detected; sync pattern occurs 588 1 efm clocks after the previous sync pattern. - a new sync pattern is detected within 6 efm clocks of its expected position. the sync coincidence signal is also used to generate the pll lock signal, which is active high after 1 sync coincidence found, and reset low if during 61 consecutive frames no sync coincidence is found. the pll lock signal can be accessed via the sda or status pins selected by register 2 and 7. also incorporated in the demodulator is a rl2 (run length 2) correction circuit. every symbol detected as rl2 will be pushed back to rl3. to do this the phase error of both edges of the rl2 symbol are compared and the correction is executed at the side with the highest error probability. 7.4.2 efm demodulation t he 14-bit efm data and subcode words are decoded into 8-bit symbols. + - dq dpll crystal clock hfin hfref iref islice v ss v dd hf input 2.2nf 2.2k w 22k w 47pf 22nf v ssa v ssa v dd /2 100nf 100 m a 100 m a figure 4 data slicer showing typical application components
philips semiconductors preliminary speci?cation: version 1.0 may 1995 11 digital servo processor and compact disc decoder (cd7) SAA7378GP figure 5 saa7378 decoder function: simplified data flow kill subcode processor error corrector fifo fade/mute/ interpolate digital filter kill phase compensation deemphasis filter iis interface ebu interface m p interface digital pll & demodulator 1 0 1 : no preemphasis detected v3 sclk wclk data reg 3 reg 3 reg c sda dobm reg a output from data slicer and reg d 1 01xx 0 : preemphasis detected or reg d = 01xx (deemphasis signal at v5)
philips semiconductors preliminary speci?cation: version 1.0 may 1995 12 digital servo processor and compact disc decoder (cd7) SAA7378GP 7.5 subcode data processing 7.5.1 q-channel processing the 96-bit q-channel word is accumulated in an internal buffer. the last 16 bits are used internally to perform a cyclic redundancy check (crc). if the data is good, the subqready-i signal will go low. subqready-i can be read via the sda or status pins, selected via register 2. good q-channel data may be read from sda. 7.5.2 subcode channels q-w data of subcode channels, q-w, is available in the ebu output (dobm). 7.6 fifo and error corrector the saa7378 has a 8 frame fifo. the error corrector is a t = 2, e = 4 type, with error corrections on both c1 (32 symbol) and c2 (28 symbol) frames. four symbols are used from each frame as parity symbols. this error corrector can correct up to two errors on the c1 level and up to four errors on the c2 level. the error corrector also contains a flag processor. flags are assigned to symbols when the error corrector cannot ascertain if the symbols are definitely good. c1 generates output flags which are read after (de-interleaving) by c2, to help in the generation of c2 output flags. the c2 output flags are used by the interpolator for concealment of uncorrectable errors. they are also output via the ebu signal (dobm). 7.6.1 flags output (cflg) the flags output pin cflg (open-drain) shows the status of the error corrector and interpolator and is updated every frame 7.35khz. in the saa7378 chip a 1-bit flag is present on the cflg pin as shown in figure 6.this signal shows the status of the error corrector and interpolator. f1 f2 f3 f4 f5 f6 f7 f1 11.3 m s 33.9 m s f8 f8 33.9 m s figure 6 flag output timing diagram
philips semiconductors preliminary speci?cation: version 1.0 may 1995 13 digital servo processor and compact disc decoder (cd7) SAA7378GP the first flag bit, f1, is the absolute time sync signal; the fifo-passed subcode-sync and relates the position of the subcode- sync to the audio data (dac output). the output flags can be made available at bit 4 of the ebu data format (lsb of the 24- bit data word), if selected by register a. 7.7 audio functions 7.7.1 deemphasis and phase linearity when pre-emphasis is detected in the q-channel subcode, the digital filter automatically includes a deemphasis filter section. when deemphasis is not required, a phase compensation filter section controls the phase of the digital oversampling filter to 1 within the band 0 - 16 khz. with deemphasis the filter is not phase linear. if the deemphasis signal is set to be available at v5, selected via register d, then the deemphasis filter is bypassed. 7.7.2 digital oversampling filter the saa7378 contains a 2 - 4 times oversampling iir ?lter. the ?lter speci?cation of the 4 x oversampling ?lter is given in the table below. these attenuations do not include the sample and hold at the external dac output or the dac post filter. when using the oversampling filter, the output level is scaled -0.5 db down, to avoid overflow on full scale sine wave inputs (0 - 20 khz). f1 f2 f3 f4 f5 f6 f7 f8 meaning 0 x x x x x x x no absolute time sync 1 x x x x x x x absolute time sync x 0 0 x x x x x c1 frame contained no errors x 0 1 x x x x x c1 frame contained 1 error x 1 0 x x x x x c1 frame contained 2 errors x 1 1 x x x x x c1 frame uncorrectable x x x 0 0 x x 0 c2 frame contained no errors x x x 0 0 x x 1 c2 frame contained 1 error x x x 0 1 x x 0 c2 frame contained 2 errors x x x 0 1 x x 1 c2 frame contained 3 error x x x 1 0 x x 0 c2 frame contained 4 errors x x x 1 1 x x 1 c2 frame uncorrectable x x x x x 0 0 x no interpolations x x x x x 0 1 x at least one 1-sample interpolation x x x x x 1 0 x at least one hold and no interpolations x x x x x 1 1 x at least one hold and one 1-sample interpolation passband attenuation 0 - 19 khz 0.001 db 19 - 20 khz 0.03 db stopband attenuation 24.0 khz 3 25 db 24 - 27 khz 3 38 db 27 - 35 khz 3 40 db 35 - 64 khz 3 50 db 64 - 68 khz 3 31 db 68 khz 3 35 db 69 - 88 khz 3 40 db
philips semiconductors preliminary speci?cation: version 1.0 may 1995 14 digital servo processor and compact disc decoder (cd7) SAA7378GP 7.7.3 concealment a 1-sample linear interpolator becomes active if a single sample is flagged as erroneous but cannot be corrected. the erroneous sample is replaced by a level midway between the preceding and following samples. left and right channels have independent interpolators. if more than one consecutive non-correctable sample is found, the last good sample is held. a 1- sample linear interpolation is then performed before the next good sample (figure 7). . 7.7.4 mute, full scale, attenuation and fade a digital level controller is present on the saa7378 which performs the functions of soft mute, full scale, attenuation and fade; these are selected via register 0. mute: signal reduced to 0 in a maximum of 128 steps; 3ms. attenuate: signal scaled by -12db. full scale: ramp signal back to 0db level. from mute takes 3ms. fade: activates a 128 stage counter which allows the signal to be scaled up/down by 0.07db steps. 128 = full scale 120 = -0.5db (ie. full scale if oversampling ?lter used) 32 = -12db 0 = mute 7.7.5 peak detector the peak detector measures the highest audio level (absolute value) on positive peaks for left and right channels. the 8 most significant bits are output in the q-channel data in place of the crc bits. bits 81 to 88 contain the left peak value (bit 88 = msb) and bits 89 to 96 contain the right peak value (bit 96 = msb). the values are reset after reading q-channel data via sda. interpolation interpolation hold ok error ok ok ok error error error figure 7 concealment mechanism
philips semiconductors preliminary speci?cation: version 1.0 may 1995 15 digital servo processor and compact disc decoder (cd7) SAA7378GP 7.8 dac interface the saa7378 is compatible with a wide range of digital-analogue converters. six formats are supported and are shown below. figure 8 and figure 9 show the philips iis and the eiaj data formats respectively. all formats are msb first and fs is 44.1khz. the polarity of the wclk and the data can be inverted; selectable by register 7. register 3 sample frequency no of bits sclk mhz format interpolation 0000 4fs 16 8.4672 * n eiaj - 16 bits yes 0100 4fs 18 8.4672 * n eiaj - 18 bits yes 1100 4fs 18 8.4672 * n philips i 2 s - 18 bits yes 0011 2fs 16 4.2336 * n eiaj - 16 bits yes 0111 2fs 18 4.2336 * n eiaj - 18 bits yes 1111 2fs 18 4.2336 * n philips i 2 s - 18 bits yes 17 0 15 sclk data wclk left channel data (wclk normal polarity) figure 8 philips i 2 s data format (18-bit word length shown ) 1 16 14 1 0 17 0 0 17 sclk data wclk left channel data figure 9 eiaj data format (18-bit word length shown)
philips semiconductors preliminary speci?cation: version 1.0 may 1995 16 digital servo processor and compact disc decoder (cd7) SAA7378GP 7.9 ebu interface the biphasemark digital output signal at pin dobm is according to the format defined by the iec958 specification. the dobm pin can be held low; selected via register a: 7.9.1 format the digital audio output consists of 32-bit words ("subframes") transmitted in biphasemark code (two transitions for a logic1 and one transition for a logic0). words are transmitted in blocks of 384. sync: the sync word is formed by violation of the biphase rule and therefore does not contain any data. its length is equivalent to 4 data bits. the 3 different sync patterns indicate the following situations: sync b:- start of a block (384 words), word contains left sample. sync m:- word contains left sample (no block start). sync w:- word contains right sample. audio sample: left and right samples are transmitted alternately. validity ?ag: audio samples are ?agged (bit 28 = 1) if an error has been detected but was uncorrectable. this ?ag remains the same even if data is taken after concealment user data: subcode bits q until w from the subcode section are transmitted via the user data bit. this data is asynchronous with the block rate. channel status: the channel status bit is the same for left and right words. therefore a block of 384 words contains 192 channel status bits. the category code is always cd. the bit assignment is shown below. 7.10 kill circuit the kill circuit detects digital silence by testing for an all-zero or all-ones data word in the left or right channel before t he digital filter. the output is switched active-low when silence has been detected for at least 250ms, or if mute is active. two modes are available, selected by register c: - 1 pin kill: kill active low indicates silence detected on both left and right channels. - 2 pin kill: kill active low indicates silence detected on left channel. v3 active low indicates silence detected on right channel. sync bits 0 - 3 auxiliary bits 4 - 7 not used. normally zero error ?ags bit 4 cflg error and interpolation ?ags when selected by register a audio sample bits 8 - 27 first 4 bits not used (always zero). 2s compliment. lsb = bit 12, msb = bit 27 validity ?ag bit 28 valid = logic 0 user data bit 29 used for subcode data (q to w) channel status bit 30 control bits and category code parity bit bit 31 even parity for bits 4 to 30 control bits 0 - 3 copy of crc checked q-channel control bits 0 - 3; bit 2 is logic 1 when copy permitted; bit 3 is logic 1 when recording has preemphasis reserved mode bits 4 - 7 always zero. category code bits 8 - 15 cd: bit 8 = logic1, all other bits = logic 0 clock accuracy bits 28 - 29 set by register a: 10 = level i 00 = level ii 01 = level iii remaining bits 16 - 27 bits 30 - 191 always zero
philips semiconductors preliminary speci?cation: version 1.0 may 1995 17 digital servo processor and compact disc decoder (cd7) SAA7378GP 7.11 the via interface the saa7378 has five pins that can be reconfigured for different applications: 7.12 spindle motor control 7.12.1 motor output modes the spindle motor speed is controlled by a fully integrated digital servo. address information from the internal 8 frame fifo and disc speed information are used to calculate the motor control output signals. several output modes, selected by register 6, are supported: - pulse density, 2-line (true complement output), 1mhz sample frequency. - pwm-output, 2-line, 22.05khz modulation frequency. - pwm-output, 4-line, 22.05khz modulation frequency. - cdv motor mode. 7.12.1.1 pulse density output mode in the pulse density mode the motor output pin, moto1, is the pulse density modulated motor output signal. 50% duty cycle corresponds with the motor not actuated, higher duty cycles mean acceleration, lower mean braking. in this mode, the moto2 signal is the inverse of the moto1 signal. both signals change state only on the edges of a 1mhz internal clock signal. possible application diagrams are shown in figure 10. 7.12.1.2 pwm output mode, 2-line in the pwm mode the motor acceleration signal is put in pulse-width modulation form on the moto1 output, and the motor braking signal is pulse-width modulated on the moto2 output. figure 11 shows the timing and figure 12 a typical application diagram. pin name pin no. type control register address control register data function v1 62 input 1100 xxx1 external offtrack signal input xxx0 internal offtrack signal used input may be read via decoder status bit; selected via register 2. v2 63 input input may be read via decoder status bit; selected via register 2. v3 42 output 1100 xx0x kill output for right channel x01x output = 0 x11x output = 1 v4 41 output 1101 0000 4-line motor drive (using v4 & v5) xx10 output = 0 xx11 output = 1 v5 40 output 1101 01xx deemphasis output (active high) 10xx output = 0 11xx output = 1
philips semiconductors preliminary speci?cation: version 1.0 may 1995 18 digital servo processor and compact disc decoder (cd7) SAA7378GP 7.12.1.3 pwm output mode, 4-line using two extra outputs from the versatile pins interface, it is possible to use the saa7378 with a 4-input motor bridge. + - m + - moto1 moto2 22 k 22 k 10n 10n v ss v ss + - v ss moto1 22 k 10 n v ss 22 k 22 k v dd m figure 10 motor pulse density application diagrams v ss v dd 22 k 22 k accelerate brake t rep = 45 m s t dead = > 240 ns moto1 moto2 figure 11 2-line pwm mode timing moto1 moto2 v ss + m figure 12 motor 2-line pwm mode application diagram 10 100n
philips semiconductors preliminary speci?cation: version 1.0 may 1995 19 digital servo processor and compact disc decoder (cd7) SAA7378GP figure 13 shows the timing, and figure 14 a typical application diagram. 7.12.1.4 cdv/cav output mode in the cdv motor mode, the fifo position will be put in pulse-width modulated form on the moto1 pin (carrier frequency 300hz), and the pll frequency signal will be put in pulse-density modulated form (carrier frequency 4.23mhz) on the moto2 pin. the integrated motor servo is disabled in this mode. notes: 1) the pwm signal on moto1 corresponds to a total memory space of 20 frames, therefore the nominal fifo position (half full) will result in a pwm output of 60%. 7.12.2 spindle motor operating modes the motor servo has the following operation modes controlled by register 1: start mode 1 disc is accelerated by applying a positive voltage to the spindle motor. no decisions are involved and the pll is reset. no disc speed information is available for the m p. start mode 2 the disc is accelerated as in start mode 1 , however the pll will monitor the disc speed. when the disc reaches 75% of its nominal speed, the controller will switch to jump mode . the motor status signals selectable via register 2 are valid. jump mode motor servo enabled but fifo kept reset at 50%, integrator is held. the audio is muted but it is possible to read the subcode. jump mode 1 similar to jump mode but motor integrator is kept at zero. used for long jumps, where there is a large change in disc speed. accelerate brake t rep = 45 m s t dead = > 240 ns moto1 moto2 t ovl = 240 ns v4 v5 figure 13 4-line pwm mode timing moto1 moto2 v4 v5 + m figure 14 motor 4-line pwm mode application diagram 10 100n v ss
philips semiconductors preliminary speci?cation: version 1.0 may 1995 20 digital servo processor and compact disc decoder (cd7) SAA7378GP play mode fifo released after resetting to 50%. audio mute released. stop mode 1 disc is braked by applying a negative voltage to the motor. no decisions are involved. stop mode 2 the disc is braked as in stop mode 1 , but the pll will monitor the disc speed. as soon as the disc reaches 12% (or 6%, depending on the programmed brake percentage, via register e) of its nominal speed, the motstop status signal will go high and switch the motor servo to off mode . off mode motor not steered. in the saa7378 decoder there is an anti-wind-up mode for the motor servo, selected via register 1. when the anti-wind-up mode is activated the motor servo integrator will hold if the motor output saturates. 7.12.2.1 power limit in start mode 1, start mode 2, stop mode 1 and stop mode 2 , a fixed positive or negative voltage is applied to the motor. this voltage can be programmed as a percentage of the maximum possible voltage, via register 6, to limit current drain during start and stop. the following power limits are possible: 100% (no power limit), 75%, 50%, or 37% of maximum. 7.12.3 loop characteristics the gain and crossover frequencies of the motor control loop can be programmed via registers 4 and 5. the following parameter values are possible: gains: 3.2, 4.0, 6.4, 8.0, 12.8, 16, 25.6, 32 crossover frequency f 4 : 0.5hz, 0.7hz, 1.4hz, 2.8hz crossover frequency f 3 : 0.85hz, 1.71hz, 3.42hz 7.12.4 fifo over?ow if fifo overflow occurs during play mode (eg: as a result of motor rotational shock), the fifo will be automatically reset to 50% and the audio interpolator tries to conceal as much as possible to minimise the effect of data loss. a f b w f 4 f 3 figure 15 motor servo bode diagram
philips semiconductors preliminary speci?cation: version 1.0 may 1995 21 digital servo processor and compact disc decoder (cd7) SAA7378GP 8. functional description of the ser vo p art 8.1 diode signal processing the photo detector in conventional two-stage three-beam compact disc systems normally contains six discrete diodes. four of these diodes (three for single focault systems) carry the central aperture (ca) signal while the other two diodes (satellite diodes) carry the radial tracking information. the ca signal is processed into an hf signal (for the decoder function) and lf signal (information for the focus servo loop) before it is supplied to the saa7378. the analog signals from the central and satellite diodes are converted into a digital representation using analog to digital converters (adcs). the adcs are designed to convert unipolar currents into a digital code. the dynamic range of the input currents is adjustable within a given range which is dependent on the value of external resistor connected to ireft. the maximum current for the central diodes and satellite diodes is given below: i in(max, central) = (2.4 * 10 6 / r ireft ) m a i in(max, satellite) = (1.2 * 10 6 / r ireft ) m a the v rh voltage is internally generated by control circuitry which takes care that the v rh voltage is adjusted depending upon the spread of internal capacitors, using the reference current generated by the external resistor on ireft. in the application v rl is connected to v ssa1 . the maximum input currents for a range of resistors is given below: this mode of v rh automatic adjustment can be selected by the preset latch command. alternatively the dynamic range of the input currents can be made dependent on the adc reference voltages; v rl and v rh , for this case the maximum current for the central diodes and satellite diodes is given below: i in(max, central) = f sys * (v rh - v rl ) * 1.0 * 10 -6 m a i in(max, satellite) = f sys * (v rh - v rl ) * 0.5 * 10 -6 m a where f sys = 4.2336mhz v rh is generated internally, and there are 32 levels which can be selected under software control, via the preset latch command. with this command the v rh voltage can be set to 2.5v then modified, decremented one level or incremented, by resending the command the required number of times. in the application v rl is connected to v ssa1 . 8.2 signal conditioning the digital codes retrieved from the adcs are applied to logic circuitry to obtain the various control signals. the signals fro m the central aperture diodes are processed to obtain a normalised focus error signal: r ireft (w) diode input current range d1,d2,d3,d4 (m a) r1,r2 (m a ) 220k 10.909 5.455 240k 10.000 5.000 270k 8.889 4.444 300k 8.000 4.000 330k 7.273 3.636 360k 6.667 3.333 390k 6.154 3.077 430k 5.581 2.791 470k 5.106 2.553 510k 4.706 2.353 560k 4.286 2.143 620k 3.871 1.935 d1 - d2 fe n = d3 - d4 - d1 + d2 d3 + d4
philips semiconductors preliminary speci?cation: version 1.0 may 1995 22 digital servo processor and compact disc decoder (cd7) SAA7378GP where the detector set up is assumed as shown in figure 16. in the case of single foucault focusing method, the signal conditioning can be switched under software control such that the signal processing is as follows: the error signal, fe n , is further processed by a proportional integral and differential (pid) filter section. a focus ok (fok) flag is generated by means of the central aperture signal and an adjustable reference level. this signal is used to provide extra protection for the track-loss (tl) generation, the focus start up procedure and the drop out detection . the radial or tracking error signal is generated by the satellite detector signals r1 and r2. the radial error signal can be formulated as follows: where the index s indicates the automatic scaling operation which is performed on the radial error signal. this scaling is necessary to avoid non-optimal dynamic range usage in the digital representation and reduces the radial bandwidth spread. furthermore, the radial error signal will be made free from offset during start up of the disc. the four signals from the central aperture detectors together with the satellite detector signals generate a track position signal (tpi), which can be formulated as follows: where the weighting factor sum_gain is generated internally, by the saa7378, during initialisation. 8.3 focus servo system the saa7378 includes the following focus servo functions: 8.3.1 focus start-up five initially loaded coefficients influence the start-up behaviour of the focus controller. the automatically generated triang le voltage can be influenced by 3 parameters; for height (ramp_height ) and dc-offset ( ramp_offset ) of the triangle and its steepness ( ramp_incr ). for protection against false focus point detections two parameters are available, which are an absolute level on the ca- signal ( ca_start ) and a level on the fe n signal ( fe_start ). when this ca level is reached the fok signal becomes true. if this fok signal is true and the level on the fe n signal is reached, the focus pid is enabled to switch on when the next zero crossing is detected in the fe n signal. figure 16 detector arrangement satellite diode r1 d2 d3 d1 single foucault satellite diode r2 satellite diode r1 d3 d2 d4 d1 satellite diode r2 satellite diode r1 d3 d2 d4 d1 satellite diode r2 astigmatic focus double foucault fe n = 2 d1 - d2 * d1 + d2 re s = (r1 - r2) * re_gain + (r1 - r2) re_offset * tpi = sign [ (d1 + d2 + d3 + d4) - (r1 + r2) sum_gain ] *
philips semiconductors preliminary speci?cation: version 1.0 may 1995 23 digital servo processor and compact disc decoder (cd7) SAA7378GP 8.3.2 focus position control loop the focus control loop contains a digital pid controller which has 5 parameters available to the user. these coefficients influence the integrating ( foc_int ), proportional (foc_lead_length, part of foc_parm3 ) and differentiating (foc_pole_lead, part of foc_parm1 ) action of the pid and a digital low pass filter (foc_pole_noise, part of foc_parm2 ) following the pid. the fifth coefficient foc_gain influences the loop gain. 8.3.3 drop-out detection this detector can be influenced by one parameter (ca_drop). the fok signal will become false and the integrator of the pid will hold if the ca signal drops below this programmable absolute ca level. when the fok signal becomes false it is assumed, initially, to be caused by a black dot. 8.3.4 focus loss detection and fast restart whenever fok is false for longer than about 3ms, it is assumed that the focus point is lost. a fast restart procedure is initia ted which is capable of restarting the focus loop within 200 to 300ms depending on the microprocessor programmed coefficients. 8.3.5 focus loop gain switching the gain of the focus control loop ( foc_gain ) can be multiplied by a factor of 2 or divided by a factor of 2 during normal operation. the integrator value of the pid is corrected accordingly. the differentiating (foc_pole_lead) action of the pid can be switched at the same time as the gain switching is performed. 8.4 radial servo system the saa7378 includes the following focus servo functions: 8.4.1 level initialisation during start-up an automatic adjustment procedure is activated to set the values of the radial error gain ( re_gain ), offset ( re_offset ) and satellite sum gain ( sum_gain ) for tpi level generation. the initialisation procedure runs in a radial open loop situation and is 300ms. this start-up time period may coincide with the last part of the motor start up time period. automatic gain adjustment: as a result of this initialisation the amplitude of the re signal is adjusted within 10% around the nominal re amplitude offset adjustment: the additional offset in re due to the limited accuracy of the start-up procedure is less than 50nm. tpi level generation: the accuracy of the initialisation procedure is such that the duty cycle range of tpi becomes 0.4 < dutycycle < 0.6 (def. dutycycle: tpi-high / tpi-period). 8.4.2 sledge control the microprocessor can move the sledge in both directions via the steer sledge command. 8.4.3 tracking control the actuator is controlled using a pid loop filter with user defined coefficients and gain. for stable operation between the tracks, the s-curve is extended over 0.75 track. upon request from the microprocessor s-curve extension over 2.25 tracks is used, automatically changing to access control when exceeding those 2.25 tracks. both modes of s-curve extension make use of a track-count mechanism. in this mode track counting results in an automatic return to zero track, to avoid major music rhythm disturbances in the audio output for improved shock resistance. the sledge is continuously controlled using the filtered value of the radial pid output. alternatively the microprocessor can read the average voltage on the radial actuator, and provides the sledge with step pulses to reduce power consumption. filter coefficients of the continuous sledge control are user presettable.
philips semiconductors preliminary speci?cation: version 1.0 may 1995 24 digital servo processor and compact disc decoder (cd7) SAA7378GP 8.4.4 access the access procedure is divided into two different modes, depending upon the requested jump size. the access procedure makes use of a track counting mechanism, a velocity signal based on a fixed number of tracks passed within a fixed time interval, a velocity setpoint calculated from the number of tracks to go and a user programmable parameter indicating the maximum sledge performance. if the number of tracks to go is greater than brake_distance then the sledge jump mode should be activated else the actuator jump should be performed. the requested jump size together with the required sledge breaking distance at maximum access speed defines the value brake_distance. during the actuator jump mode, velocity control with a pi controller is used for the actuator. the sledge is then continuously controlled using the filtered value of the radial pid output. all filter parameters (for actuator and sledge) are user programmable. in sledge jump mode maximum power (user programmable) is applied to the sledge in the correct direction, while the actuator becomes idle (the contents of the actuator integrator leaks to zero just after the sledge jump mode is initiated). 8.5 off t rack counting the track position (tpi) signal is a flag which is used to indicate whether the radial spot is positioned on the track, with a margin of 1/4 of the track-pitch. in combination with the radial polarity flag (rp) the relative spot position over the tracks can be determined. these signals are, however afflicted with some uncertainties caused by: ? disc defects such as scratches and ?ngerprints. ? the hf information on the disc, which is considered as noise by the detector signals. in order to determine the spot position with sufficient accuracy, extra conditions are necessary to generate a track loss (tl) signal as well as an off-track counter value. these extra conditions influence the maximum speed and this implies that, internally, one of the three following counting states is selected: 1. protected state: used in normal play situations. a good protection against false detection caused by disc defects is important in this state. 2. slow counting state: used in low velocity track jump situations. in this state a fast response is important rather than the protection against disc defects (if the phase relationship between tl and rp of 1/2 p radians is affected too much, the direction cannot be determined accurately anymore). 3. fast counting state: used in high velocity track jump situations. highest obtainable velocity is the most important feature in this state. 8.6 defect detection a defect detection circuit is incorporated into the saa7378. if a defect is detected, the radial and focus error signals may be zeroed, resulting in better playability. the defect detector can be switched off, applied only to focus control, or applied to both focus and radial controls under software control (part of foc_parm1 ). the defect detector (figure 17) has programmable setpoints selectable by the parameter, defect_parm . access type jump size access speed actuator jump 1 - brake_distance 1 decreasing velocity sledge jump brake_distance 1 - 32768 maximum power to sledge 1 1 : microprocessor presettable figure 17 defect detector block diagram sat1 + - fast decimation defect programmable hold-off sat2 slow defect out filter filter filter generation +
philips semiconductors preliminary speci?cation: version 1.0 may 1995 25 digital servo processor and compact disc decoder (cd7) SAA7378GP 8.7 off t rack detection during active radial tracking, off track detection has been realised by continuously monitoring the off track counter value. the off track flag becomes valid whenever the off track counter value is unequal to zero. depending on the type of extended s-curve the off track counter is reset after 0.75 extend or at the original track in the 2.25 track extend mode. 8.8 driver interface the control signals (pins ra, fo and sl) for the mechanism actuators are pulse density modulated. the modulating frequency can be set to either 1.0584mhz (dsd mode) or 2.1168mhz; controlled via the xtra_preset parameter. an analog representation of the output signals can be achieved by connecting a first order low pass filter to the outputs. during reset (ie. reset pin is held low) the ra, fo and sl pins are high impedance. 8.9 laser interface the ldon pin (open drain output) is used to switch the laser off and on; when the laser is on the output is high impedance. the action of the ldon pin is controlled by the xtra_preset parameter; the pin is automatically driven if the focus control loop is active. 8.10 radial shock detector the shock detector (block diagram shown in figure 18) can be switched on during normal track following; and detects within an adjustable frequency whether disturbances in the radial spot position relative to the track exceed an adjustable level (controlled by shock_level ). every time the radial tracking error (re) exceeds this level the radial control bandwidth is switched to twice its original bandwidth and the loop gain is increased by a factor of 4. the shock detection level is adjustable in 16 steps from 0 to 100% of the traverse radial amplitude which is sent to an amplitude detection unit via an adjustable bandpass filter (controlled by sledge_parm1 ); lower corner frequency can be set at either 0 or 20hz, and upper corner frequency at 750 or 1850hz. the shock detector is switched off automatically during jump mode. figure 18 block diagram of shock detector re high pass filter amplitude shock (0 or 20hz) low pass filter (750 or 1850hz) detection out
philips semiconductors preliminary speci?cation: version 1.0 may 1995 26 digital servo processor and compact disc decoder (cd7) SAA7378GP 9. microprocessor interf ace communication on the microprocessor interface is via a 4-wire bus: the protocol being compatible with saa7345 (cd6) and tda1301 (dsic2): scl - serial bit clock. sda - serial data. rab - r/w control and data strobe (active high) for writing to registers 0 - f, reading status bit selected via register 2 and reading q channel subcode. sild - r/w control and data strobe (active low) for servo commands. 9.1 w riting data to registers 0 - e the sixteen 4-bit programmable configuration registers, 0 to e (table 1), can be written to via the microprocessor interface using the protocol shown in figure 19. note that: - sild must be held high. - a(3:0) identifies the register number, d(3:0) is the data. - the data is latched into the register on the low-high transition of rab. 9.1.1 writing repeated data to registers 0 - e the same data can be repeated several times (eg: for a fade function) by applying extra rab pulses as shown in figure 20. note that scl must stay high between rab pulses. 9.2 reading decoder status information on sda there are several internal status signals, selected via register 2, which can be made available on the sda line. these are: - subqready-i low if new subcode word is ready in q-channel register. - motstart1 high if motor is turning at 75% or more of nominal speed. - motstart2 high if motor is turning at 50% or more of nominal speed. - motstop high if motor is turning at 12% or less of nominal speed. can be set to indicate 6% or less (instead of 12% or less) via register e. - pll lock high if sync coincidence signals are found. - v1 follows input on v1 pin. rab ( m p) scl ( m p) sda ( m p) sda (saa7378) hi-impedance a3 a2 a1 a0 d3 d2 d1 d0 figure 19 microprocessor write protocol for registers 0 to e rab ( m p) scl ( m p) sda ( m p) sda (decoder) hi-impedance a3 a2 a1 a0 d3 d2 d1 d0 figure 20 microprocessor write protocol for registers 0 to e - repeat mode
philips semiconductors preliminary speci?cation: version 1.0 may 1995 27 digital servo processor and compact disc decoder (cd7) SAA7378GP - v2 follows input on v2 pin. - motor-ov high if the motor servo output stage saturates. - fifo-ov high if fifo over?ows. - shock motstart2 + pll lock + motor-ov + fifo-ov + otd (high if shock detected) - la-shock latched shock signal the status read protocol is shown in figure 21. note that: - sild must be held high. 9.3 reading q-channel subcode to read q-channel subcode direct in 4-wire bus mode, the subqready-i signal should be selected as status signal. the subcode read protocol is shown in figure 22 . note that: - sild must be held high. - after subcode read starts, the microprocessor may take as long as it wants to terminate the read operation. - when enough subcode has been read (1 - 96 bits), terminate reading by pulling rab low. 9.3.1 behaviour of the subqready-i signal when the crc of the q-channel word is good, and no subcode is being read, the subqready-i status signal will react as shown in figure 23 : rab ( m p) scl ( m p) sda ( m p) sda (saa7378) hi-impedance status figure 21 microprocessor read protocol for decoder status on sda rab ( m p) scl ( m p) sda (saa7378) q1 q2 q3 qn-2 qn-1 qn crc ok status figure 22 microprocessor protocol for reading q-channel subcode
philips semiconductors preliminary speci?cation: version 1.0 may 1995 28 digital servo processor and compact disc decoder (cd7) SAA7378GP when the crc is good and subcode is being read, the timing in figure 24 applies : if t 1 ( subqready-i status low to end of subcode read) is below 2.6ms, then t 2 = 13.1ms [ie: the microprocessor can read all subcode frames if it completes the read operation within 2.6ms after the subcode is ready]. if this criterion is not met, i t is only possible to guarantee that t 3 will be below 26.2ms (approximately). if subcode frames with failed crcs are present, the t 2 and t 3 times will be increased by 13.1ms for each defective subcode frame. 9.4 w rite servo commands a write data command is used to transfer data (a number of bytes) from the microprocessor, using the protocol shown in figure 25. the first of these bytes is the command byte and the following are data bytes; the number (between 1 and 7) depends on the command byte. note that: - rab must be held low. - the command or data is interpreted by the saa7378 after the high-low transition of sild. - there must be a minimum time of 65 m s between sild pulses. 9.4.1 writing repeated data in servo commands the same data byte can be can be repeated by applying extra sild pulses as shown in figure 26. scl must stay high rab ( m p) scl ( m p) sda (saa7378) read start allowed 10.8ms 15.4ms 2.3 ms crc ok crc ok high impedance figure 23 subqready-i status timing when no subcode is read rab ( m p) scl ( m p) sda (saa7378) q1 q2 q3 qn t 2 t 1 t 3 figure 24 subqready-i status timing when subcode is read
philips semiconductors preliminary speci?cation: version 1.0 may 1995 29 digital servo processor and compact disc decoder (cd7) SAA7378GP between the sild pulses. 9.5 read servo commands a read data command is used to transfer data (status information) to the microprocessor, using the protocol shown in figure 27. the first byte written determines the type of command. after this byte a variable number of bytes can be read. note that: - rab must be held low. - after the end of a read command there must be a delay of 65 m s before a write command is started. - there must be a minimum time of 65 m s between sild pulses. figure 25 microprocessor protocol for write servo commands sild ( m p) scl ( m p) sda ( m p) sda (saa7378) hi-impedance d7 d6 d5 d4 d3 d2 d1 d0 command or data byte sild ( m p) command data1 data2 data3 sda ( m p) microprocessor write (one byte : command or data) microprocessor write (full command) sda ( m p) figure 26 microprocessor protocol for repeated data in write servo commands sild ( m p) command data1 microprocessor write (full command) sild ( m p) scl ( m p) sda ( m p) d7 d6 d5 d4 d3 d2 d1 d0 figure 27 microprocessor protocol for read servo commands data byte sda (saa7378) command sda (saa7378) microprocessor read (one data byte) microprocessor read (full command) sild ( m p) data1 data2 data3
philips semiconductors preliminary speci?cation: version 1.0 may 1995 30 digital servo processor and compact disc decoder (cd7) SAA7378GP 9.6 summary of functions controlled by registers 0 to e the initial column shows the power-on reset state table 1 registers 0 to e register address data function initial 0 0000 0000 mute reset (fade and 0010 attenuate attenuation) 0001 full scale 0100 step down 0101 step up 1 0001 x000 motor off mode reset (motor mode) x 0 0 1 motor stop mode 1 x 0 1 0 motor stop mode 2 x 0 1 1 motor start mode 1 x 1 0 0 motor start mode 2 x 1 0 1 motor jump mode x 1 1 1 motor play mode x 1 1 0 motor jump mode 1 1 x x x anti-windup active 0 x x x anti-windup off reset 2 0010 0000 status = subqready-i reset (status control) 0001 status = motstart1 0010 status = motstart2 0011 status = motstop 0100 status = pll lock 0101 status = v1 0110 status = v2 0111 status = motor-ov 1000 status = fifo over?ow 1001 status = shock detect 1010 status = latched shock detect 1011 status = latched shock detect reset 3 0011 1100 i 2 s - 18 bit - 4fs mode reset (dac output) 1111 i 2 s - 18 bit - 2fs mode 0000 eiaj - 16 bit - 4fs 0011 eaij - 16 bit - 2fs 0100 eiaj - 18 bit - 4fs 0111 eiaj - 18 bit - 2fs
philips semiconductors preliminary speci?cation: version 1.0 may 1995 31 digital servo processor and compact disc decoder (cd7) SAA7378GP register address data function initial 4 0100 x000 motor gain g = 3.2 reset (motor gain) x 0 0 1 motor gain g = 4.0 x 0 1 0 motor gain g = 6.4 x 0 1 1 motor gain g = 8.0 x 1 0 0 motor gain g = 12.8 x 1 0 1 motor gain g = 16.0 x 1 1 0 motor gain g = 25.6 x 1 1 1 motor gain g = 32.0 0 x x x disable comparator clock divider reset 1 x x x enable comparator clock divider; only if sellpll set high 5 0101 xx00 motor f 4 = 0.5hz reset (motor bandwidth) x x 0 1 motor f 4 = 0.7hz x x 1 0 motor f 4 = 1.4hz x x 1 1 motor f 4 = 2.8hz 0 0 x x motor f 3 = 0.85hz reset 0 1 x x motor f 3 = 1.71hz 1 0 x x motor f 3 = 3.42hz 6 0110 xx00 motor power max. 37% reset (motor output x x 0 1 motor power max. 50% con?guration) x x 1 0 motor power max. 75% x x 1 1 motor power max. 100% 0 0 x x moto1, moto2 pins tri-state reset 0 1 x x motor pwm mode 1 0 x x motor pdm mode 1 1 x x motor cdv mode 7 0111 x000 dac data normal value reset (dac output) x 1 0 0 dac data inverted value 0 x x x l channel ?rst at dac (wclk normal) reset 1 x x x r channel ?rst at dac (wclk inverted) loop bw hz int. bw hz low-pass bw hz 8 1000 0000 1640 525 8400 (pll loop ?lter 0001 3279 263 16800 bandwidth) 0010 6560 131 33600 0100 1640 1050 8400 0101 3279 525 16800 0110 6560 263 33600 1000 1640 2101 8400 1001 3279 1050 16800 reset 1010 6560 525 33600 1100 1640 4200 8400 1101 3279 2101 16800 1110 6560 1050 33600 table 1 registers 0 to e
philips semiconductors preliminary speci?cation: version 1.0 may 1995 32 digital servo processor and compact disc decoder (cd7) SAA7378GP register address data function initial 9 1001 0011 pll loop ?lter equalisation reset (pll equalisation) 0001 pll 30ns over-equalisation 0010 pll 15ns over-equalisation 0100 pll 15ns under-equalisation 0101 pll 30ns under-equalisation a 1010 x010 level ii clock accuracy (<1000ppm) reset (ebu output) x 0 1 1 level i clock accuracy (<50ppm) x 1 1 0 level iii clock accuracy (>1000ppm) x 1 1 1 ebu off - output low 0 x x x flags in ebu off reset 1 x x x flags in ebu on b 1011 00xx 33.8688mhz crystal present, or 8.4672mhz crystal with selpll set high reset 0 1 x x 16.9344mhz crystal present x x 0 0 standby 1 : cd-stop mode reset x x 1 0 standby 2 : cd-pause mode x x 1 1 operating mode c 1100 xxx1 external offtrack signal input at v1 (versatile pins xxx0 internal offtrack signal used (v1 may be read via status) reset interface) x x 0 x kill-l at kill output, kill-r at v3 output 001x v3 = 0; single kill output reset 011x v3 = 1; single kill output d 1101 0000 4-line motor (using v4, v5) (versatile pins x x 1 0 v4 = 0 interface) x x 1 1 v4 = 1 reset 0 1 x x de-emphasis signal at v5, no internal de-emphasis ?lter 1 0 x x v5 = 0 1 1 x x v5 = 1 reset e 1110 0100 motor brakes to 12% reset 0101 motor brakes to 6% table 1 registers 0 to e
philips semiconductors preliminary speci?cation: version 1.0 may 1995 33 digital servo processor and compact disc decoder (cd7) SAA7378GP 9.7 summary of servo commands a list of the servo commands are given below; note that these are not fully backwards compatible with dsic2: table 2 cd7 servo commands. write commands code bytes parameters write_focus_coefs1 17h 7 write_focus_coefs2 27h 7 write_focus_command 33h 3 focus_gain_up 42h 2 focus_gain_down 62h 2 write_radial coefs 57h 7 preset_latch 81h 1 radial_off c1h 1 "1ch" radial_init c1h 1 "3ch" short_jump c3h 3 long_jump c5h 5 steer_sledge b1h 1 preset_init 93h 3 write_parameter a2h 2 read commands code bytes parameters read_status 70h up to 5 read_aux_status f0h up to 3
philips semiconductors preliminary speci?cation: version 1.0 may 1995 34 digital servo processor and compact disc decoder (cd7) SAA7378GP 9.7.1 summary of servo command parameters a list of the servo command parameters are given below: parameter ram addr. affects por value determines foc_parm_1 - focus pid end of focus lead defect detector enabling foc_parm_2 - focus pid focus low pass focus error normalising foc_parm_3 - focus pid focus lead length minimum light level foc_int 14h focus pid focus integrator crossover freq foc_gain 15h focus pid 70h focus pid loop gain ca_drop 12h focus pid sensitivity of drop-out detector ramp_offset 16h focus ramp assymetry of focus ramp ramp_height 18h focus ramp p-p value of ramp voltage ramp_incr - focus ramp slope of ramp voltage fe_start 19h focus ramp minimum value of focus error rad_parm_play 28h radial pid end of radial lead rad_pole_noise 29h radial pid radial low-pass rad_length_lead 1ch radial pid length of radial lead rad_int 1eh radial pid radial integrator crossover freq rad_gain 2ah radial pid 70h radial loop gain rad_parm_jump 27h radial jump ?lter during jump vel_parm1 1fh radial jump pi controller crossover freqs vel_parm2 32h radial jump jump pre-de?ned pro?le speed_threshold 48h radial jump maximum speed in fastrad mode hold_mult 49h radial jump 00h sledge bandwidth during jump brake_dist_max 21h radial jump max sledge distance allowed in fast actuator steered mode sledge_long_brake 58h radial jump 7fh brake distance of sledge sledge_umax - sledge voltage on sledge during long jump sledge_level - sledge voltage on sledge when steered sledge_parm_1 36h sledge sledge integrator crossover freq sledge_parm_2 17h sledge sledge low pass freqs sledge gain sledge operation mode defect_parm - defect detector defect detector setting shock_level - shock detector shock detector operation chip_init - setup v rh level setting xtra_preset 4ah setup 38h laser on/off ra, fo, sl pdm modulating freq. con?g_parm1 42h setup initialisation con?g_parm2 53h setup initialisation con?g_parm3 59h setup initialisation con?g_parm4 68h setup initialisation
philips semiconductors preliminary speci?cation: version 1.0 may 1995 35 digital servo processor and compact disc decoder (cd7) SAA7378GP 10. opera ting characteristics 10.1 general characteristics v dd = 3.4 to 5.5 v; v ss = 0; t amb = 5 to 70 c; unless otherwise stated. symbol parameter conditions min typ max unit supply v dd supply voltage 3.4 5.0 5.5 v i dd supply current v dd = 5 v - 49 ma decoder analogue front-end (v dd = 5.0 v; v ss = 0; t amb = 25 c) comparator inputs, hfin, hfref: f comp clock frequency see note 1 8 - 70 mhz v th switching thresholds 1.2 - v dd - 0.8 v v tpt hfin input level 1.0 - v reference generator, iref: v iref reference voltage at iref pin - v dd /2 - v servo analogue part (v dd = 5.0 v; v ss = 0; t amb = 25 c) pins d1, d2, d3, d4, r1, r2, vrh, vrl, ireft: i ireft input current for ireft 1.935 - 5.45 m a r ireft external resistor on ireft 220 - 620 k w v ireft voltage on current input ireft - 1.2 - v i d maximum input current for central diode input signal see note 2 3.871 - 10.9 m a i r maximum input current for satellite diode input signal see note 2 1.935 - 5.45 m a v rl low level reference voltage 0 0 0 v v rh high level reference voltage see note 3 output state 0 - 0.5 - v output state v -30% .5*10 v/44.4 +30% v output state 31 - 2.5 - v (thd+n)/s total harmonic distortion plus noise at 0 db; see note 5 - -50 -45 db s/n signal to noise ratio - 55 - db psrr power supply rejection at v dda 2 see note 4 - 45 - db g tol gain tolerance see note 6 -12 0 +12 % d g variation of gain between channels - - 2 % a channel separation - 60 - d b
philips semiconductors preliminary speci?cation: version 1.0 may 1995 36 digital servo processor and compact disc decoder (cd7) SAA7378GP symbol parameter conditions min typ max unit digital inputs i nput: reset, v1, v2, selpll cmos input with pullup and hysteresis v thr switching threshold rising - - 0.8 x v dd v v thf switching threshold falling 0.2 x v dd --v v hys hysteresis voltage - 0.33 x v dd -v r pu input pull-up resistance v in = 0 - 50 - k w c in input capacitance - - 10 pf t rw reset pulse width (active low) reset only 1 - - m s input: scl, rab, sild cmos input v il input voltage low -0.3 - 0.3 x v dd v v ih input voltage high 0.7 x v dd -v dd + 0.3 v i in input leakage current v in = 0 - v dd -10 - +10 m a c in input capacitance - - 10 pf digital output outputs: cl4 v ol output voltage low i ol = + 1 ma 0 - 0.4 v v oh output voltage high i oh = - 1 ma v dd - 0.4 - v dd v c l load capacitance - - 25 pf t r output rise time (c l = 20 pf) 0.8 to (v dd - 0.8) - - 20 ns t f output fall time (c l = 20 pf) (v dd - 0.8) to 0.8 - - 20 ns outputs: cl16 v ol output voltage low i ol = +1 ma 0 - 0.4 v v oh output voltage high i oh = -1 ma v dd - 0.4 - v dd v c l load capacitance - - 50 pf t r output rise time (c l = 20 pf) 0.8 - (v dd - 0.8) - - 15 ns t f output fall time (c l = 20 pf) (v dd - 0.8) - 0.8 - - 15 ns outputs: v4, v5 v ol output voltage low (v dd = 4.5 to 5.5 v) i ol = + 10 ma 0 - 1.0 v output voltage low (v dd = 3.4 to 5.5 v) i ol = + 5 ma 0 - 1.0 v v oh output voltage high (v dd = 4.5 to 5.5 v) i oh = -10 ma v dd - 1 - v dd v output voltage high (v dd = 3.4 to 5.5 v) i oh = -5 ma v dd - 1 - v dd v c l load capacitance - - 50 pf t r output rise time (c l = 20 pf) 0.8 - (v dd - 0.8) - - 10 ns t f output fall time (c l = 20 pf) (v dd - 0.8) -0.8 - - 10 ns
philips semiconductors preliminary speci?cation: version 1.0 may 1995 37 digital servo processor and compact disc decoder (cd7) SAA7378GP open drain outputs outputs: cflg, status, kill, v3, ldon open drain output with protection diode to vdd v ol output voltage low i ol = +1 ma 0 - 0.4 v i ol output current - - 2 ma c l load capacitance - - 25 pf t f output fall time (c l = 20 pf) (v dd - 0.8) - 0.8 - - 30 ns tri-state outputs outputs: sclk, wclk, data, cl11 v ol output voltage low i ol = +1 ma 0 - 0.4 v v oh output voltage high i oh = -1 ma v dd - 0.4 - v dd v c l load capacitance - - 50 pf t r output rise time (c l = 20 pf) 0.8 - (v dd - 0.8) - - 15 ns t f output fall time (c l = 20 pf) (v dd - 0.8) - 0.8 - - 15 ns i in tri-state leakage current v in = 0 - v dd -10 - +10 m a output: cl11 t high output high time (relative to clock period) v o = 1.5 v 45 50 55 % outputs: ra, fo, sl v ol output voltage low i ol = +1 ma 0 - 0.4 v v oh output voltage high i oh = -1 ma v dd - 0.4 - v dd v c l load capacitance - - 25 pf t r output rise time (c l = 20 pf) 0.8 - (v dd - 0.8) - - 20 ns t f output fall time (c l = 20 pf) (v dd - 0.8) - 0.8 - - 20 ns i in tri-state leakage current v in = 0 - v dd -10 - +10 m a outputs: moto1, moto2, dobm v ol output voltage low (v dd = 4.5 to 5.5 v) i ol = +10 ma 0 - 1.0 v output voltage low (v dd = 3.4 to 5.5 v) i ol = +5 ma 0 - 1.0 v v oh output voltage high (v dd = 4.5 to 5.5 v) i oh = -10 ma v dd - 1 - v dd v output voltage high (v dd = 3.4 to 5.5 v) i oh = -5 ma v dd - 1 - v dd v c l load capacitance - - 50 pf t r output rise time (c l = 20 pf) 0.8 - (v dd - 0.8) - - 10 ns t f output fall time (c l = 20 pf) (v dd - 0.8) -0.8 - - 10 ns i in tri-state leakage current v in = 0 - v dd - 10 - +10 m a symbol parameter conditions min typ max unit
philips semiconductors preliminary speci?cation: version 1.0 may 1995 38 digital servo processor and compact disc decoder (cd7) SAA7378GP notes: 1) highest clock frequency at which data slicer produces 1010 output in analogue self-test mode. 2) v rl = 0v, f sys =4.2336mhz. the maximum input current depends on the value of the external resistor connected to ireft. for d1 to d4: i max = 2.4 / r ireft t 2.4 / 220k = 10.9 m a. for r1 and r2: i max = 1.2 / r ireft t 1.2 / 220k = 5.45 m a. 3) internal reference source with 32 different output voltages. selection is achieved during a calibration period or via the serial interface. the values given are for an unloaded v rh . 4) f ripple = 1 khz, v ripple = 0.5 v p-p . 5) v rh = 2.5 v and v rl = 0 v, measuring bandwidth: 200 hz - 20 khz, f in(adc) = 1 khz. 6) gain of the adc is de?ned as : g(adc) = f sys /i max (counts/ m a) thus digital output = i i x g(adc) where: digital output = the number of pulses at the digital output in counts/s and i i = the dc input current in m a. the maximum input current depends on the system frequency (f sys =4.2336mhz) and on v rh - v rl . the gain tolerance is the deviation from the calculated gain regarding note 2. 7) it is recommended that the series resistance of the crystal or ceramic resonator is 60 w . symbol parameter conditions min typ max unit digital input/output input/output: sda cmos input/open drain output (with protection diode to vdd) v il input voltage low -0.3 - 0.3 x v dd v v ih input voltage high 0.7 x v dd -v dd + 0.3 v i in tri-state leakage current v in = 0 - v dd -10 - +10 m a c in input capacitance - - 10 pf v ol output voltage low i ol = +2 ma 0 - 0.4 v i ol output current - - 4 ma c l load capacitance - - 50 pf t f output fall time (c l = 20 pf) (v dd - 0.8) - 0.8 - - 15 ns crystal oscillator input: crin (external clock) v il input voltage low -0.3 - 0.3 x v dd v v ih input voltage high 0.7 x v dd -v dd + 0.3 v i in input leakage current -10 - +10 m a c in input capacitance - - 10 pf output: crout see figure 3 fc crystal frequency see note 7 8 8.4672 35 mhz g m mutual conductance at 100khz - 10 - ma/v a v small signal voltage gain a v = g m * r o -18- v/v c f feedback capacitance - - 5 pf c out output capacitance - - 10 pf
philips semiconductors preliminary speci?cation: version 1.0 may 1995 39 digital servo processor and compact disc decoder (cd7) SAA7378GP 10.2 operating characteristics (i2s t iming) v dd = 3.4 to 5.5 v; v ss = 0; t amb = 5 to 70 c; unless otherwise stated. symbol parameter conditions min typ max unit i 2 s timing; see figure 28 clock output: sclk (c l = 20pf) t po output clock period sample rate = fs sample rate = 2 fs sample rate = 4 fs - - - 472.4 236.2 118.1 - - - ns ns ns t hc clock high time sample rate = fs sample rate = 2 fs sample rate = 4 fs 166 83 42 - - - - - - ns ns ns t lc clock low time sample rate = fs sample rate = 2 fs sample rate = 4 fs 166 83 42 - - - - - - ns ns ns outputs: wclk, data, ef (cl = 20pf) t st setup time sample rate = fs sample rate = 2 fs sample rate = 4 fs 95 48 24 - - - - - - ns ns ns t ht hold time sample rate = fs sample rate = 2 fs sample rate = 4 fs 95 48 24 - - - - - - ns ns ns figure 28 i 2 s timing 0.8 v v dd -0.8 v v dd -0.8 v 0.8 v clock period t po t hc t lc t ht t st sclk wclk data ef
philips semiconductors preliminary speci?cation: version 1.0 may 1995 40 digital servo processor and compact disc decoder (cd7) SAA7378GP 10.3 operating characteristics ( m p interface t iming) v dd = 3.4 to 5.5 v; v ss = 0; t amb = 5 to 70 c; unless otherwise stated. notes: 1) negative set-up time means that the data may change after clock transition. symbol parameter conditions min typ max unit m p interface timing (writing to registers 0 to f; reading q-channel subcode and decoder status) see figure 29 and figure 30. inputs scl and rab t l input low time 500 - - ns t h input high time 500 - - ns t r rise time - - 480 ns t f fall time - - 480 ns read mode (cl = 20pf) t drd delay time rab to sda valid - - 50 ns t dd propagation delay scl to sda 700 - 980 ns t drz delay time rab to sda hi-impedance - - 50 ns write mode (cl = 20pf) t sd setup time sda to scl note 1 -700 - - ns t hd hold time scl to sda - - 980 ns t scr setup time scl to rab 260 - - ns t dwz delay time sda hi-impedance to rab 0 - - ns m p interface timing (servo commands) see figure 31 and figure 32. inputs scl and sild t l input low time 710 - - ns t h input high time 710 - - ns t r rise time - - 240 ns t f fall time - - 240 ns read mode (cl = 20pf) t dld delay time sild to sda valid - - 25 ns t dd propogation delay scl to sda - - 950 ns t dlz delay time sild to sda hi-impedance - - 50 ns write mode (cl = 20pf) t sd set up time sda to scl 0 - - ns t hd hold time scl to sda 950 - - ns t scl aet up time scl to sild 480 - - ns t hcl hold time sild to scl 120 - - ns t plp delay between two sild pulses 65 - - m s t dwz delay time sda hi-impedance to sild 0 - - ns
philips semiconductors preliminary speci?cation: version 1.0 may 1995 41 digital servo processor and compact disc decoder (cd7) SAA7378GP figure 29 microprocessor timing (q-channel subcode and decoder status information) - read mode rab scl sda (saa7378) t drz t drd t dd 0.8 v 0.8 v v dd - 0.8 v v dd - 0.8 v v dd - 0.8 v 0.8 v t r t r t f t f figure 30 microprocessor timing (registers 0 to e) - write mode rab scl sda( m p) t sd 0.8 v 0.8 v v dd - 0.8 v v dd - 0.8 v t hd t scr t l v dd - 0.8 v t dwz t l t h 0.8 v t h figure 31 microprocessor timing (servo commands) - read mode sild scl sda (saa7378) t dlz t dld t dd 0.8 v 0.8 v v dd - 0.8 v v dd - 0.8 v
philips semiconductors preliminary speci?cation: version 1.0 may 1995 42 digital servo processor and compact disc decoder (cd7) SAA7378GP figure 32 microprocessor timing (servo commands) - write mode sild scl sda( m p) t plp t sd 0.8 v 0.8 v v dd - 0.8 v v dd - 0.8 v t hd t scl t l v dd - 0.8 v t hcl t dwz t l t h 0.8 v
philips semiconductors preliminary speci?cation: version 1.0 may 1995 43 digital servo processor and compact disc decoder (cd7) SAA7378GP 11. applica tion informa tion figure 33 typical saa7378 application diagram saa7378 v ssa 1 v dda 1 d1 d2 d3 v rl d4 r1 r2 ireft v rh v ssa 2 selpll islice hfin v ssa 3 v2 v1 cflg test10 v dd 3 c test9 reset v ss 4 41 sild rab scl sda cl4 ldon hfref iref v dda 2 test1 crin crout test2 cl16 cl11 ra fo sl test3 v dd 1 p dobm sclk v dd 2 p wclk data test8 kill v3 v4 v5 v ss 2 test7 test6 test5 test4 moto2 moto1 v ss 3 v ss 1 33 39 37 34 47 44 43 40 38 36 35 48 46 45 42 8 16 10 12 15 2 5 6 9 11 13 14 1 3 4 7 24 32 26 28 31 18 21 22 25 27 29 30 17 19 20 23 57 49 55 53 50 63 60 59 56 54 52 51 64 62 61 58 + v v dda + 2.2 w 100nf 33 m f 220pf 220pf 220pf 100k w 100k w 220pf 220pf 220pf v dda 100nf 22nf 100nf 47pf 22k w 270k w 2.2k w 2.2nf to power amplifiers to dobm transformer micro-controller interface to dac 100nf motor interface v dd + v + v + v v dd v dd 2.2 w 33 m f + 4.7k w 4.7k w 100nf 2.2 w 100nf 2.2 w 100nf (1) (2) d4 3 rfe d2 d3 d1 d5 d6 ldon 2 5 4 9 1 6 7 tda1300 (1) diagram is for a 5v application. for 3.4v applications an additional resistor of 150k w should be added between iref (pin 18) and ground. (2) for crystal oscillator circuit see figure 3. (3) the connections to tda1300 are shown for single foucault mechanisms. (3)
philips semiconductors preliminary speci?cation: version 1.0 may 1995 44 digital servo processor and compact disc decoder (cd7) SAA7378GP 12. p ackage outline figure 34 64-lead quad flat-pack; plastic (sot393-1)
philips semiconductors preliminary speci?cation: version 1.0 may 1995 45 digital servo processor and compact disc decoder (cd7) SAA7378GP 13. soldering 13.1 plastic quad ?at-packs 13.1.1 by w a ve during placement and before soldering, the component must be fixed with a droplet of adhesive. after curing the adhesive, the component can be soldered. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. maximum permissible solder temperature is 260 o c, and maximum duration of package immersion in solder bath is 10 s, if allowed to cool to less than 150 o c within 6 s. typical dwell time is 4 s at 250 o c. a modified wave soldering technique is reccommended using two solder waves (dual-wave), in which a turbulent wave with high upward pressure is followed by a smooth laminar wave. using a mildly-activated flux eliminates the need for removal of corrosive residues in most applications. 13.1.2 by solder p aste reflow reflow soldering requires the solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the substrate by screen printing, stencilling or pressure-syringe dispensing before device placement. several techniques exist for reflowing; for example, thermal conduction by heated belt, infrared, and vapour-phase reflow. dwell times vary between 50 and 300 s according to method. typical reflow temperatures range from 215 to 250 o c. prehaeting is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 min at 45 o c. 13.1.3 rep airing soldered joints (by hand-held soldering iron or pulse-hea ted solder t ool) fix the component by first soldering two, diagonally opposite, end pins. apply the heating tool to the flat part of the pin onl y. contact time must be limited to 10 s at up to 300 o c. when using proper tools, all other pins can be soldered in one operation within 2 to 5 s at between 270 and 320 o c. (pulse-heated soldering is not recommended for so packages.) for pulse-heated solder tool (resistance) soldering of vso packages, solder is applied to the substrate by dipping or by an extra thick tin/lead plating before package placement. 14. definitions 15. life support applica tions these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values are given in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation.

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